Highly efficient capacitor structures with enhanced matching properties

ABSTRACT

The present specification discloses highly efficient capacitor structures. One embodiment of the present invention is referred to herein as a vertical parallel plate (VPP) structure. In accordance with this embodiment, a capacitor structure comprises a plurality of vertical plates. The vertical plates are substantially parallel to each other, and each vertical plate comprises multiple conducting strips. These conducting strips are substantially parallel to each other and are connected to each other by one or more vias. The vertical plates are alternately connected to each other, creating a first portion of the vertical plates and a second portion of the vertical plates, such that the first portion of the vertical plates forms a first terminal of the capacitor structure, and the second portion of the vertical plates forms a second terminal of the capacitor structure. Either slotted vias or individual vias can be used to connect the conducting strips.  
     Another embodiment of the present invention is referred to herein as a vertical bars (VB) structure. In accordance with this embodiment of the present invention, a capacitor structure comprises a plurality of rows of vertical bars, wherein within each row, the vertical bars are parallel to each other, and each vertical bar comprises multiple conducting patches. These conducting patches are connected to each other by one or more vias. The rows of vertical bars form a first direction and a second direction, wherein the second direction is orthogonal to the first direction. In the first direction, the vertical bars are alternately connected to each other, creating a first portion of the vertical plates and a second portion of the vertical plates. The first portion of the vertical plates forms a section of the first terminal of the capacitor structure, and the second portion of the vertical plates forms a section of the second terminal of the capacitor structure. In the second direction, the vertical bars are alternately connected to each other, creating a third portion of the vertical plates and a fourth portion of the vertical plates. The third portion of the vertical plates forms a remaining section of the first terminal of the capacitor structure, and the fourth portion of the vertical plates forms a remaining section of the second terminal of the capacitor structure. Either slotted vias or individual vias can be used to connect the conducting strips.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This invention claims the benefit of Provisional Application No.60/232,651, filed on Sep. 14, 2000. The contents of that application areincorporated by reference herein.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention generally relates to using lateral fieldcapacitor structures to increase the capacitance density per unit areain integrated circuit capacitors, and in particular to using novellateral-field optimal high efficient capacitor structures that maximizethe flux usage in the interlayer metal separation region, as well as, inthe metal layer region.

[0004] 2. Description of Related Art

[0005] Capacitors are essential elements in integrated circuits, such assample and holds, analog-to-digital (A/D) and digital-to-analog (D/A)converters, switched-capacitor and continuous-time filters, as well as,radio frequency (RF) blocks. In many of these applications, capacitorsconsume a large portion of a chip's area. Thus, the capacitor's areaefficiency is of primary importance. In analog applications, the otherdesired properties for capacitors are close matching of adjacentcapacitors, linearity, small bottom-plate capacitor, and to a lesserdegree, the absolute accuracy of the value (i.e., tolerance). In RFapplications, it is essential for the capacitors to have self-resonancefrequencies, well in excess of the frequency of interest and largequality factors (Q). Good linearity and large breakdown voltage are theother two desired properties for a good RF capacitor.

[0006] Several approaches have been taken to improve the area efficiencyof capacitors. For example, nonlinear capacitors with high capacitancedensity, such as junction or gate oxide capacitors have been used for along time in applications where the linearity and the quality factor, Q,of the capacitors are not important. Unfortunately, these capacitorsneed a dc bias and are strongly process and temperature dependent. Inhigh precision circuits, such as data converters, their use is limitedto bypass and coupling capacitors, or varactors in RF circuits.

[0007] On the other hand, metal- to-metal and metal-to-poly capacitorshave very good linearity and quality factors, Q. However, they sufferfrom a low capacitance density. The low capacitance density manly arisesfrom large metal-to-metal/metal-to-poly vertical spacing that determinesthe capacitance in the horizontal parallel plate (HPP) structure 100,shown in FIG. 1. Unfortunately, in today's process technologies, thislarge vertical spacing does not shrink as fast as the lateral separationto avoid excessive crosstalk between the digital metal lines indifferent layers. Thus, the parallel plate capacitors consume a largerfractional die area. Although an extra processing step involvingdepositing a thin layer of insulator between two metal or poly layerscan mitigate the vertical spacing problem to some extent, this extrastep is not available in many of the standard silicon-basedtechnologies. Even if such special capacitor layers were available, theparallel plate structure does not necessarily result in the highestpossible capacitance density

[0008] The capacitance density can be improved by structures thatexploit both lateral and vertical electric field components. A wellknown example of such structures is the interdigitated parallel wirestructure 200 (also know as Horizontal Bars or HB), as shown in FIG. 2.Recently, several new structures were suggested as methods of obtaininghigher capacitance per unit area. These structures include: aquasi-fractal structure 208; a woven structure 202 connected using vias210 (the top view 204 of the woven structure 202 is also shown); and asecond woven structure 206 without via 210 interconnections. The newstructures 200, 202, 206, and 208 essentially demonstrate the samelinearity as the HPP structure 100 (shown in FIG. 1), including both themetal-to-metal/poly capacitors. The only difference between the newstructures 200, 202, 206, and 208 and the HPP structure 100 (shown inFIG. 1) is the higher capacitance densities. These structures 200, 202,206, and 208 also provide lower bottom-plate capacitance, since morefield lines end up on the adjacent metal line, as opposed to thesubstrate

[0009] Despite these advantages, quasi-fractal structures 208 and wovenstructures 202 and 206 have not been widely used in the signal path ofanalog circuits because predicting their absolute capacitor value can becomplicated and time consuming. Also, it is not clear that thequasi-fractal structures 208 and woven structures 202 and 206 are alwaysadvantageous over the more regular structures, such as theinterdigitated parallel wire structures 200.

[0010] Thus, there is a need in the art for new capacitor structureswith high efficiency, which demonstrate higher capacitance density andsuperior matching properties, as compared to the standard HPP structures100 (shown in FIG. 1) and previously reported quasi fractal structures208 (shown in FIG. 2) and woven structures 202 and 206 (shown in FIG.2).

SUMMARY OF THE INVENTION

[0011] To overcome the limitations in the prior art described above, andto overcome other limitations that will become apparent upon reading andunderstanding the present specification, the specification disclosesseveral capacitor structures that demonstrate high capacitance density,superior matching, tolerances, and self-resonance frequencies.

[0012] The first embodiment of the present invention is referred toherein as a vertical parallel plate (VPP) structure. In accordance withthe first embodiment, a capacitor structure comprises a plurality ofvertical plates. The vertical plates are substantially parallel to eachother, and each vertical plate comprises multiple conducting strips.These conducting strips are substantially parallel to each other and areconnected to each other by one or more vias. The vertical plates arealternately connected to each other, creating a first portion of thevertical plates and a second portion of the vertical plates, such thatthe first portion of the vertical plates forms a first terminal of thecapacitor structure, and the second portion of the vertical plates formsa second terminal of the capacitor structure. Either slotted vias,interleaving vias or individual vias can be used to connect theconducting strips.

[0013] The second embodiment of the present invention is referred toherein as a vertical bars (VB) structure. In accordance with the secondembodiment of the present invention, a capacitor structure comprises aplurality of rows of vertical bars, wherein within each row, thevertical bars are parallel to each other, and each vertical barcomprises multiple conducting patches. These conducting patches areconnected to each other by one or more vias. The rows of vertical barsform a first direction and a second direction, wherein the seconddirection is orthogonal to the first direction. In the first direction,the vertical bars are alternately connected to each other, creating afirst portion of the vertical plates and a second portion of thevertical plates. The first portion of the vertical plates forms asection of the first terminal of the capacitor structure, and the secondportion of the vertical plates forms a section of the second terminal ofthe capacitor structure. In the second direction, the vertical bars arealternately connected to each other, creating a third portion of thevertical plates and a fourth portion of the vertical plates. The thirdportion of the vertical plates forms a remaining section of the firstterminal of the capacitor structure, and the fourth portion of thevertical plates forms a remaining section of the second terminal of thecapacitor structure.

[0014] Each patch has a lateral size. The lateral size affects theeffective series resistance of the capacitor structure. The lateral sizealso affects the quality factor of the capacitor structure.

[0015] The fourth embodiment is similar to the first embodiment, and itis referred to herein as a two-layer VPP. The two-layer VPP structurecomprises two VPP structures, wherein the first VPP is positioned in afirst direction. The second VPP is located on top of the first VPP, andthe second VPP is positioned in a second direction The second directionis orthogonal to the first direction.

[0016] The fifth embodiment is also similar to the first embodiment, andit is referred to herein as a multiple-layer VPP. The multiple-layer VPPstructure comprises multiple (more than two) VPP structures, wherein aprevious VPP is positioned in a first direction. A subsequent VPP islocated on top of the previous VPP, and the subsequent VPP is positionedin a second direction. The second direction is orthogonal to the firstdirection.

[0017] Each of the above-described embodiments have utility forproviding a capacitor structure with high efficiency, which results inhigher capacitance density and superior matching and toleranceproperties, as compared to prior art capacitor structures.

BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Referring now to the drawings in which like reference numbersrepresent corresponding parts throughout:

[0019]FIG. 1 represents a prior art parallel plate structure;

[0020]FIG. 2 represents prior art structures that exploit both lateraland vertical electrical fields;

[0021]FIG. 3 represents an exemplary vertical parallel plate (VPP)structure, in accordance with the present invention;

[0022]FIG. 4 represents an exemplary vertical parallel plate (VPP)structure implemented using stacked vias, in accordance with the presentinvention;

[0023]FIG. 5 represents an exemplary vertical parallel plate (VPP)structure implemented using interleaved vias, in accordance with thepresent invention;

[0024]FIG. 6 represents an exemplary vertical bar (VB) structure, inaccordance with the present invention;

[0025]FIG. 7 represents an exemplary modified VB structure, inaccordance with the present invention;

[0026]FIG. 8 represents an exemplary two-layer VPP structure, inaccordance with the present invention;

[0027]FIG. 9 represents an exemplary multi-layer VPP structure, inaccordance with the present invention;

[0028]FIG. 10 shows a graph of simulated capacitance densities per unitvolume as a function of minimum lateral spacing;

[0029]FIG. 11 represents the dimensions of the metal lines;

[0030]FIG. 12 shows parallel plate structures normal to the cartesianaxis;

[0031]FIG. 13 represents the ortho-normal capacitance decomposition intolateral and vertical parallel plates,

[0032]FIG. 14 shows the relative capacitance variations of the VPP, HB,and HPP structures;

[0033]FIG. 15 shows a graph of the high-frequency one-port measurementsof the VPP structure, the VB structure, and the HPP structure; and

[0034]FIG. 16 shows the relative capacitance variations of the VPP, VBand HPP structures.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMNETS

[0035] Several lateral-field, optimal-high efficient capacitorstructures are described. Each of these capacitor structures maximizesthe flux usage in the interlayer metal separation region, as well as, inthe metal layer region.

[0036]FIG. 3 illustrates a capacitor structure that is referred toherein as a vertical parallel plate (VPP) structure 300. The VPPstructure 300 has several vertical plates 302. Each of the verticalplates 302 are substantially parallel to each other, and located apredefined lateral distance from an adjacent vertical plate 302.

[0037] The vertical plates 302 comprise multiple conducting strips 306.The conducting strips 306 can be either metal conducting strips or polycrystalline silicon strips. The conducting strips 306 are substantiallyparallel to each other, and they are connected to each other by one ormore vias 304. The vias 304 can either be slotted vias, interleavingvias or individual vias.

[0038] The vertical plates 302 are alternately connected, such that allthe shaded vertical plates 302 are connected to each other, creating afirst portion of the vertical plates 302; and all the clear verticalplates 302 are connected to each other, creating a second portion of thevertical plates 302. The first portion of the vertical plates 302 form aterminal of the capacitor structure, and the second portion of thevertical plates 302 form the other terminal of the capacitor structure.

[0039] To simplify the explanation of the figures and to show theterminals of the capacitors, some of the vertical plates 302 in FIG. 3are shaded. Similar shading is used in FIG. 4 through FIG. 9. Thisshading does not, in any way, limit or restrict the scope of the presentinvention.

[0040] The VPP structure 300 maximizes the lateral flux usage by usingvertical plates 302 made out of conducting strips 306. The conductingstrips 306 are connected by using vias 304 that maximize the lateralarea of the vertical plates 302. The via 304 interconnections increasethe effective lateral area of the vertical plates 302, and lowers theseries electrical resistance by the introduction of alternative currentpaths, resulting in a higher quality factor, Q, for a given capacitorvalue. Moreover, due to the current flowing in opposite direction in thevertical plates 302, the inherent inductance is decreased. Also, as theVPP structure 300 attains higher capacitance density, smaller physicaldimensions are achieved for a given capacitor value, thus, resulting ina shorter average signal path, and therefore, having a higherself-resonance frequency. Even though slotted vias 304 may not besupported in all process technologies, close approximation to thesestructures can be fabricated by using individual vias 304, as shown inFIG. 4 or using interleaving vias 304, as shown in FIG. 5. The top metallayer, which is usually thicker, and has different design rules, can beused to make the connection between the capacitor terminal and outsidecircuitry. Low series resistance is assured by the multiple placement ofvias 304 and several signal path cross-connections.

[0041]FIG. 6 illustrates a structure, referred to herein as a verticalbar (VB) structure 600. The VB structure 600 has several rows ofvertical bars 602. The vertical bars 602 are substantially parallel toeach other, and the vertical bars 602 are located at a predefinedlateral distance from each other.

[0042] Each vertical bar 602 has multiple conducting patches 604 (orsquares). The conducting patches 604 can be metal conducting patches orpoly-crystalline silicon conducting patches. Each of the conductingpatches 604 have a lateral size. The lateral size affects the effectiveseries resistance of the capacitor structure 600. The lateral size alsoaffects the quality factor, Q, of the capacitor structure 600. Theconducting patches 604 are connected to each other by one or more vias606. The vias 606 can be either slotted via or individual vias.

[0043] The length of the vertical bars 602 is limited by the number andthickness of metal layers. The VB structure 600 can show a larger seriesresistance compared to the VPP 300 structure. However, the seriesresistance of the. VB structure 600 is mainly determined by the viaresistance. A large number of small capacitors in parallel form thetotal capacitance of the structure, and hence, the overall seriesresistance is the parallel combination of these resistors, which will bemuch smaller than an individual via 606.

[0044] The VB structure 600 has a higher capacitance density than theVPP structure 400 because the VB structure 600 utilizes the electricfield in both the lateral and vertical dimensions. To illustrate, inFIG. 6, arrow 608 represents the lateral direction and arrow 610represents the vertical direction. It is noted that the lateraldirection is orthogonal to the vertical direction. In the lateraldirection, the vertical bars 602 are alternately connected, such thatall the shaded vertical bars 602 are connected to each other, creating afirst portion of the vertical bars 602; and all the clear vertical bars602 are connected to each other, creating a second portion of thevertical plates 602. The first portion of the vertical bars 602 form asection of the first terminal of a capacitor structure, and the secondportion of the vertical bars 602 form the other terminal of thecapacitor structure.

[0045] In the vertical direction, the vertical bars 602 are alternatelyconnected, such that all the shaded vertical bars 602 are connected toeach other, creating a third portion of the vertical bars 602; and allthe clear vertical bars 602 are connected to each other, creating afourth portion of the vertical plates 602. The third portion of thevertical bars 602 form the remaining section of the first terminal ofthe capacitor structure, and the fourth portion of the vertical bars 602form the remaining section of the other terminal of the capacitorstructure.

[0046] To simplify the explanation of the figures, and for illustrationpurposes only, some of the vertical bars 602 in FIG. 6 are shaded. Thisshading does not in any way limit or restrict the scope of the presentinvention.

[0047]FIG. 7 illustrates another structure, referred to herein as amodified VB structure 700. The modified VB structure 700 extends thewidth of the vertical bars in one lateral dimension and is a compromisebetween the VPP structure 300 (shown in FIG. 3) and the VB structure 600(shown in FIG. 6). Like the VB structure 600, the modified VB structure700 utilizes the electric field in both the lateral and verticaldirections, therefore the modified VB structure 700 has a highercapacitance density than the VPP structure 300. For the modified VBstructure 700, the lateral size of each square 704 affects the effectiveseries resistance of the modified VB structure 700. The lateral size ofeach square 704 also affects the quality factor, Q, of the modified VBstructure 700.

[0048]FIG. 8 illustrates the fourth structure, referred to herein as atwo-layer vertical parallel plate VPP structure 800. The two-layer VPPstructure 800 comprises two VPP structures 802, wherein the first VPPstructure 802 is positioned in a first direction. The second VPPstructure 802 is located on top of the first VPP structure 802, and thesecond VPP sructure 802 is positioned in a second direction. The seconddirection is orthogonal to the first direction. It is noted that the twoVPP structures 802 can have different types of vias 804. For example,the first VPP structure 802 could have individual vias 804, and thesecond VPP structure 802 could have interleaving vias 804. Of course,those skilled in the art will recognize that any combination of viatypes could be used without exceeding the scope of the presentinvention.

[0049]FIG. 9 illustrates a fifth structure, referred to herein as amultiple-layer vertical parallel plate VPP structure 900. Themultiple-layer VPP structure 900 comprises multiple (more than two) VPPstructures 902, wherein a previous VPP structure 902 is positioned in afirst direction. A subsequent VPP structure 902 is located on top of theprevious VPP structure 902, and the subsequent VPP structure 902 ispositioned in a second direction. The second direction is orthogonal tothe first direction. The VPP structures 902 are positioned on top ofeach other in the above-described manner, until all of the VPPstructures 902 have been stacked. It is noted that each VPP structure902 can have different types of vias 904 or each VPP structure 902 canhave the same type of vias 904. In FIG. 9, each of the VPP structures902 have slotted vias 904. Those skilled in the art will recognize thatany combination of vias 904 can be used without departing from the scopeof the present invention.

[0050] The capacitor value of the standard, horizontal parallel platecapacitor 100 of FIG. 1 is primarily determined by the oxide thickness.On the other hand, the exact capacitor values of the VPP 300 and VB 600capacitor structures are determined by lithography and etching. Thesetwo processes are quite accurate in today's process technologies. It istherefore reasonable to suspect that the lateral component of thesecapacitors should be more repeatable and have smaller variation across awafer. In this case, it is clear that any structure combining thelateral and vertical field component will suffer from the accuracy ofthe vertical capacitance component, which will lead to inferior matchingand tolerance properties. Practically, all of the existing integratedcapacitive structures use the vertical fields, and hence, cannot achievethe best possible accuracy. This hypothesis can be verifiedexperimentally, as discussed later.

[0051] To gain more insight into the effectiveness of lateral andvertical field usage in metal-to-metal capacitor structures, thecapacitance densities for each of the capacitor structures discussedabove were simulated using a simulator developed for this purpose, andassuming a larger number of metal layers. FIG. 10 shows a graph 1000 ofthe simulation results. The horizontal axis 1002 represents the minimumlateral dimensions, and the vertical axis 1004 represents thecapacitance per unit volume.

[0052] The simulated structures include the following: the HPP structure100 (shown in FIG. 1), the VPP structure 300 (shown in FIG. 3), thewoven structure 202 and the woven structure without vias 206 (both shownin FIG. 2), parallel wires 200 (also referred to as interdigitated andHB, shown in FIG. 2), the quasi-fractal structure 208 (shown in FIG. 2),and the VB structure 600 (shown in FIG. 6), and the Cubes 3D structure(not shown).

[0053] A theoretical framework is necessary to understand the comparisonof the various capacitor structures. The following paragraphs willreveal that the capacitance of any arbitrary capacitive structure can bedecomposed into three components that are associated with threeorthogonal spatial dimensions. This decomposition can be used to findthe theoretical upper bounds for the total capacitance of rectangular(Manhattan) structures. This can be done by noting that the totalelectrostatic energy, U_(E), in a capacitor, C, is given by$\begin{matrix}{U_{E} = \frac{{C \cdot \Delta}\quad V^{2}}{2}} & (1)\end{matrix}$

[0054] where ΔV is the voltage drop across its two terminals. Thecapacitance of an arbitrary structure can be calculated by integratingthe electrostatic energy density, u, over the entire dielectric volumeto obtain the total stored electrostatic energy, U_(E), for a givenvoltage drop, ΔV, between the two terminals of the capacitor, i.e.,$\begin{matrix}{C = {\frac{2 \cdot U_{E}}{\Delta \quad V^{2}} = {\frac{2}{\Delta \quad V^{2}}{\int_{Vol}{{u\left( \overset{\rightarrow}{r} \right)}{v}}}}}} & (2)\end{matrix}$

[0055] where {right arrow over (r)} is the position vector and dv is thedifferential unit of volume. For an isotropic dielectric material, theelectrostatic energy density is given by $\begin{matrix}{{u\left( \overset{\rightarrow}{r} \right)} = {\frac{{\overset{\rightarrow}{E}\left( \overset{\rightarrow}{r} \right)} \cdot {\overset{\rightarrow}{D}\left( \overset{\rightarrow}{r} \right)} \cdot {\overset{\rightarrow}{D}\left( \overset{\rightarrow}{r} \right)}}{2} = {{\frac{ɛ_{0}ɛ_{r}}{2}{E^{2}\left( \overset{\rightarrow}{r} \right)}} = {{\frac{ɛ_{0}ɛ_{r}}{2}\left\lbrack {{E_{x}^{2}\left( \overset{\rightarrow}{r} \right)} + {E_{y}^{2}\left( \overset{\rightarrow}{r} \right)} + {E_{z}^{2}\left( \overset{\rightarrow}{r} \right)}} \right\rbrack} = {{u_{x}\left( \overset{\rightarrow}{r} \right)} + {u_{y}\left( \overset{\rightarrow}{r} \right)} + {u_{z}\left( \overset{\rightarrow}{r} \right)}}}}}} & (3)\end{matrix}$

[0056] where {right arrow over (E)} and {right arrow over (D)} are theelectric and displacement vectors, ε₀ is the permittivity of free space,ε_(r) is the relative permittivity of the dielectric, and u_(x), u_(y),and u_(z) are the electrostatic energy densities due to the electricfield components along the three Cartesian axes, namely, E_(x), E_(y),and E_(z) respectively. Therefore, the density (capacitance per unitvolume) can be calculated by integrating the sum of the threeelectrostatic field energy density components over the dielectricvolume, i.e., $\begin{matrix}{c = {\frac{C}{Vol} = {{\frac{1}{Vol} \cdot {\frac{2}{\Delta \quad V^{2}}\left\lbrack {{\int_{Vol}{{u_{x}\left( \overset{\rightarrow}{r} \right)}{v}}} + {\int_{Vol}{{u_{y}\left( \overset{\rightarrow}{r} \right)}{v}}} + {\int_{Vol}{{u_{z}\left( \overset{\rightarrow}{r} \right)}{v}}}} \right\rbrack}} = {c_{x} + c_{y} + c_{z}}}}} & (4)\end{matrix}$

[0057] where c is the capacitance density of the structure (in Farad percubic meter) and c_(x), c_(y), and c_(z) are the capacitance densitiesdue to the electric field components E_(x), E_(y), and E_(z),respectively.

[0058] Now consider a process technology with a minimum lateral spacingof L_(min) 1100, minimum metal width of W_(min) 1102, a vertical spacingbetween two adjacent metal layers, t_(ox) 1104 and a metal thickness,t_(metal) 1106 as shown in FIG. 11. The total capacitance density, c,cannot exceed the sum of the maximums of its individual components,namely, c_(x,max), c_(y,max), and c_(z,max). In other words, we have tomaximize the capacitance density due to each component of the electricfield separately, to obtain an upper bound on the density. FIG. 12 showsthat the capacitance contribution of the electric field along the xaxis, c_(x), (with no constraint on the contributions of other fieldcomponents) can be maximized by using a parallel plate structure 1200with minimum plate thickness, W_(min) 1202, and minimum spacing, L_(min)1204, perpendicular to the x axis. The capacitive components along they,and z axes can be maximized in a similar fashion by using minimumspacing parallel plate structures normal to these axes (1206 and 1208).Therefore, an upper bound on the total capacitance density can beobtained by adding the individual maximums of the capacitance densitycomponents, i.e., $\begin{matrix}{c_{\max} = {{c_{x,\max} + c_{y,\max} + c_{z,\max}} = {ɛ_{0}{ɛ_{r}\left\lbrack {\frac{2}{L_{\min}\left( {L_{\min} + W_{\min}} \right)} + \frac{1}{t_{ox}\left( {t_{ox} + t_{metal}} \right)}} \right\rbrack}}}} & (5)\end{matrix}$

[0059] This is a capacitance per unit volume, and can be easilytranslated to capacitance per unit area for a known number of metallayers. This maximum in the capacitance density will be referred to asTheoretical Limit 1 (TL1). Equation (5) defines an upper bound for thecapacitance density of any metallic structure and can serve as areference for comparison of various capacitive structures.

[0060] Although the horizontal and vertical parallel plate capacitorstructures of FIG. 12 have the maximum horizontal and vertical fieldusage, respectively, they cannot be implemented in the same spatiallocation simultaneously. This makes it impossible to achieve the maximumelectric field usage in the x, y, and z dimensions at the same time, andtherefore equation (5), while being correct, is too conservative. Theorthogonality of the electric field components implies that thehorizontal and vertical parallel plate capacitance densities, c_(x),c_(y), and c_(z) may form an orthogonal basis for decomposition ofcapacitance densities as illustrated in FIG. 13. This orthogonaldecomposition can be used to obtain a new tighter upper bound for thecapacitance density of structures with rectangular (Manhattan)boundaries. FIG. 13 shows that the maximum capacitance is given by themagnitude of the vector sum of c_(x,max), c_(y,max), and c_(z,max). Themaximum capacitance density for any given process technology will begiven by: $\begin{matrix}{c_{\max} = {\sqrt{c_{x,\max}^{2} + c_{y,\max}^{2} + c_{z,\max}^{2}} = {ɛ_{o}ɛ_{r}\sqrt{\frac{2}{{L_{\min}^{2}\left( {L_{\min} + W_{\min}} \right)}^{2}} + \frac{1}{{t_{ox}^{2}\left( {t_{ox} + t_{metal}} \right)}^{2}}}}}} & (6)\end{matrix}$

[0061] which will be referred to as Theoretical Limit 2 (TL2).

[0062] Returning to FIG. 10, the graph 1000 shows the simulatedcapacitance densities per unit volume as a function of the minimumlateral spacing, L_(min). Equal lateral metal spacing 1100 and width1102 (both shown in FIG. 11) was assumed, i.e., L_(min)=W_(min). Botht_(ox) 1104 and t_(metal) 1106 (both shown in FIG. 11) are also keptconstant at 8 μm. This is in accordance with the observation thatlateral spacings keep scaling down as lithography advances, while thevertical dimensions do not scale at the same rate. Even though the graph1000 is for particular values of t_(ox) 1104 and t_(metal) 1106, it caneasily be used for other vertical spacings through a simple scaling, aslong as, t_(ox)=t_(metal) and L_(min)=W_(min). TL1 1006 and TL2 1008 arealso plotted in the graph 1000. As can be seen, none of the capacitancedensities exceed either TL1 1006 or TL2 1008.

[0063] Two important regions can be identified in the simulation resultsof FIG. 10. For large lateral spacings, i.e., L_(min)>>t_(ox) (righthand side of the graph 1000), the capacitance density reaches plateausas the lateral fields become inconsequential and the capacitance isdominated by the vertical fields. As can be seen, the HPP structure 1010has the best performance in this region due to its optimal usage ofvertical fields, and the VPP 1012 and VB 1014 continuously degrade dueto the lack of any vertical field component. Other structures fall inbetween these two extremes and reach a capacity limit controlled bytheir vertical-to-lateral field usage efficiency.

[0064] At the other extreme, when the minimum lateral spacing is muchsmaller than the vertical separation, i.e. L_(mim)<<t_(ox) (left handside of the graph), the capacitance densities of the lateral fieldstructures become inversely proportional to L_(min) ² because thelateral plate spacing decreases linearly with lateral shrinkage,resulting in a linear increase in the capacitance per plate. Inaddition, the number of plates per unit volume grows linearly withdecreasing L_(min) due to the smaller metal width and spacing, resultingin an inverse L_(min) ² dependence. It is therefore desirable to choosea capacitor with maximum lateral field usage, as the feature sizesshrink. Such a choice will result in a capacitor with minimum verticalfield usage due to the inherent trade-off between lateral and verticalfield utilization. In other words, the lateral field usage can only beincreased by introducing dielectric regions between metal lines in thesame layer, which in turn results in loss of the vertical component. Ascan be seen, the HPP structure 1010 has the worst performance in thisregion, and the VPP 1012 and VB 1014 attain the highest capacitancedensity.

[0065] In particular, for the case where L_(min)=W_(min)=0.1 μm andt_(ox)=t_(metal)=1 μm (or for any other case where the minimum lateraldimensions are ten times smaller than the vertical dimensions), VB 1014and VPP 1012 achieve a remarkable capacitance density of 88% and 68%when compared to TL2 1008. In contrast, the woven 1018 and quasi-fractalstructure 1016 show only an efficiency of 48% and 25% respectively.Therefore, TL2 1008 can be used as a means of efficiency comparison.

[0066] A two metal layer CMOS technology with an additional thick metallayer is used to fabricate the VPP 300, interdigitated or HorizontalBars (HB) 200 and HPP 100 structures that occupy 0.12 mm², 0.33 mm²,and0.19 mm², respectively. The two lower metal layers haveL_(min)=W_(min)=0.5 μm, t_(ox)=0.95 μm, and t_(metal)=0.63 μm. Theperformance numbers for these structures are summarized in Table 1. Ascan be seen, the VPP capacitor achieves a factor of 4.4 capacitancedensity improvement over the standard HPP using only two metal layers,but also for equal capacitance values demonstrate a higherself-resonance frequency than the HPP structure. This is based on thesize-normalized self-resonance frequencies of the structures listed inTable 1. In terms of series resistance, the VPP capacitor has a seriesresistance, r_(s), of 0.57 Ω comparable to an r_(s) of 0.55 Ω for theHPP capacitor (shown in FIG. 1). It is noteworthy that the commonly usedinterdigitated (or HB) structure 200 (shown in FIG. 2) is inferior tothe newly introduced VPP capacitor 300 (shown in FIG. 3), in capacitancedensity, quality factor, and self-resonance frequency.

[0067] To investigate the tolerance properties of the VPP capacitor 300(shown in FIG. 3), the capacitance of these three structures weremeasured across twenty-two different sites, at different locations, ontwo quarters of two different 8-inch wafers. In FIG. 14, a histogram1400 shows the relative capacitance value distribution across one of thequarter-wafers. The standard deviations of the capacitance, normalizedto the average value for these three structures, are also shown inTable 1. It can be easily seen that the absolute capacitance accuracy ofthe VPP 300 capacitor is approximately an order of magnitude better thanthe conventional HPP 100. Comparison of the measurements on twodifferent wafers also shows that wafer-to-wafer capacitance variation ofthe purely lateral structures is also improved significantly due to thehigher repeatability of the lithography. Finally, due to the highbreakdown voltage of the dielectric, the measured breakdown voltages ofthe implemented capacitors are in excess of 350V, as can be seen in theTable 1. TABLE 1 Measurement Results (First Set) Structure Cap.Density(c) [aF/μm²] Ave (C_(ave)) [pF] Std. Dev. (σ_(c)) [fF]$\frac{\sigma_{c}}{C_{ave}}$

f_(res)[GHz] Q @1 GHz $\begin{matrix}{res}^{{({{fixed}\quad L})}^{a}} \\\left( {C = {6.94\quad {pF}}} \right) \\\lbrack{GHz}\rbrack\end{matrix}\quad$

$\begin{matrix}f_{res}^{{({{scaled}\quad L})}^{b}} \\\left( {C = {6.94\quad {pF}}} \right) \\\lbrack{GHz}\rbrack\end{matrix}\quad$

Rs (Ω) Break- Down [Volts] VPP 158.3 18.99 103 0.0054 3.65 14.5 6.049.99 0.57 355 HB 101.5 33.5 315 0.0094 1.1 8.6 2.42 5.31 0.55 380 HPP35.8 6.94 427 0.0615 6.0 21 6.0 6.0 1.1 690

[0068] A second set of capacitors were fabricated in a purely digitalCMOS 5-metal layer process technology with L_(min)=W_(min)=0.24 μm,t_(ox)=0.7 μm, and t_(metal)=0.53 μm. The implemented capacitors includea 5 metal layer HPP 100, a 5 metal layer VPP 300, and a 4 metal layermodified VB 700 structures. To perform a fair comparison, the value ofthe three different capacitor types are designed to be equal. A 1 pF anda 10 pF version of each structure were fabricated in the same die toprovide an unbiased comparison of the structures' capacitance density,self-resonant frequency, tolerance and matching properties.

[0069] The summary of the measurements for the 1 pF capacitors are shownin Table 2. For the sake of comparison, the performance measures of a 1pF Metal-Insulator-Metal (MIM) capacitor are also included in Table 2.Due to the lack of any MIM capacitor in the purely digital CMOStechnology used, these performance measures are obtained from the designmanual information for an MIM capacitor for a very similar processtechnology with L_(min)=0.28 μm and mixed signal capabilities.

[0070] Due to the high lateral field efficiency of the new proposedstructures, the VPP 300 and VB 600 capacitors show 7.43 and 6.29 timesmore capacitance density than the standard multiplate HPP 100 of FIG. 1,respectively, which are the highest reported to date. This correspondsto a capacitance density of 1.51 fF/μm². As can be seen, the capacitancedensity of the VPP capacitor is even 37% higher than the capacitancedensity of the MIM capacitor. TABLE 2 Measurement Results (Second Set -1 pF capacitors) Structure Cap.Density (c) [aF/μm²] Ave C_(ave)) [pF]Area [μm²] Cap. Enhancement Std. Dev. (σ_(c)) [fF]$\frac{\sigma_{c}}{C_{ave}}$

f_(res)[GHz] $\frac{{Measured}\quad Q}{{@\quad 1}\quad {GHz}}$

Break- Down [Volts] V 1512.2 1.01 669.9 7.4 5.06 0.0050 >40 83.2 128 VB1281.3 1.07 839.7 6.3 14.19 0.0132 37.1 48.7 124 HPP 203.6 1.09 5378.21.0 26.11 0.0238 21 63.8 500 MIM 1100 1.05 960.9 5.4 11 95

[0071] Because of the multiple via connections and the large number ofvertical plates connected in parallel, the VPP 300 structure presents aquality factor even higher than that of the HPP 100, whereas the qualityfactor of the VB 600 structure is degraded to some extent because of therelatively high via resistance of the process technology, as summarizedin Table 2.

[0072] As the proposed structures attain higher capacitance densities,their physical dimensions are smaller and hence show higherself-resonance frequencies. The admittance vs frequency measurement 1500of FIG. 15 shows a self-resonance frequency in excess of 40 GHz for the1 pF VPP 1502 and VB 1504 capacitors. This is twice the self-resonancefrequency of the HPP capacitor 1506, and 4 times higher than that of theMIM capacitor.

[0073] To verify the earlier hypothesis of better tolerance and matchingproperties of the purely lateral structures, the capacitance ofcapacitors of same values implemented using different structures weremeasured across 37 usable sites of an 8-inch wafer. The standarddeviation normalized to the average value of each 1 pF structure isshown in Table 2. The histogram 1600 of FIG. 16 shows the variation ofthe three different capacitor structures across the wafer. As can beseen, the VPP 300 structure presents almost five times bettercapacitance tolerance than the HPP 100 structure across the wafer.

[0074] Although the tolerance of capacitors is an important property toquantify, in many analog applications, the parameter of moresignificance is the ratio between two adjacent capacitors. To confirmthe better matching properties of the new structures, the ratio ofadjacent 10 pF and 1 pF capacitors of the same type, on the same site,were compared across the wafer. The variations of this ratio normalizedto its average is shown as σ_(r)/r_(ave). The VPP 300, VB 600, and HPP100 capacitors show a σ_(r)/r_(ave) of 0.6%, 1%, and 1.3%, respectively.Due to the higher accuracy of the lithography process, the two newlateral field structures present better matching properties than thestandard horizontal parallel plate capacitor or HPP 100, as suggestedearlier. It is noteworthy that in practice, an accurately defined ratiois achieved by using multiple parallel capacitors of the same size andshape.

[0075] Finally, the summary of the measurements for the 10 pF capacitorsare shown in Table 3. For the sake of comparison, Table 3 also includesthe estimated performance measures of a 10 pF MIM capacitor. As can beseen, the VPP 300 and VB 600 capacitors show 8.0 and 6.6 times morecapacitance density than the 10 pF standard multiplate HPP 100 ofFIG. 1. This corresponds to a 34% higher capacitance density of the VPP300 capacitor when compared to the MIM. The self-resonance frequenciesof the proposed structures are in excess of 11 GHz, which is almosttwice the self-resonance frequency of the HPP 100 capacitor, andapproximately 3 times higher than that of the MIM. As can be seen, the10 pF VPP 300 and VB 600 capacitors presents almost 3 times bettercapacitance tolerance than the HPP 100 structure across the wafer. TABLE3 Measurement Results (Second Set - 10 pF capacitors) StructureCap.Density (c) [aF/μm²] Ave C_(ave)) [pF] Area [μm²] Cap. EnhancementStd. Dev. (σ_(c)) [fF] $\frac{\sigma_{c}}{C_{ave}}$

f_(res)[GHz] $\frac{{Measured}\quad Q}{{@\quad 1}\quad {GHz}}$

Break- Down [Volts] VPP 1480.0 11.46 7749 8.0 73.43 0.0064 11.3 26.6 125VS 1223.2 10.60 8665 6.6 73.21 0.0069 11.1 17.8 121 HPP 183.6 10.2155615 1.0 182.14 0.0178 6.17 23.5 495 MIM 1100 10.13 9216 6.0 4.05 25.6

[0076] A new theoretical framework which shows the capacity limits ofdifferent capacitor structures was presented. This new framework can beused to evaluate the performance of the existing capacitive structuresand leads to two purely lateral capacitor structures, namely VPP 300 andVB 600. These structures demonstrate: higher capacitance density, bettertolerance and matching properties, and higher self-resonance frequencythan previously reported capacitor structures, MIN and standard HPPcapacitors, while maintaining a comparable quality factor. These two newstructures are standard CMOS compatible and do not need an extraprocessing step, as is the case with special MIM capacitors.

[0077] Although the invention has been described in detail withreference only to the presently preferred embodiments, those of ordinaryskill in the art will appreciate that various modifications can be madewithout departing from the invention. Accordingly, the invention isdefined only by the following claims.

What is claimed:
 1. A capacitor structure, comprising: a plurality ofvertical plates, wherein the vertical plates are substantially parallelto each other, and wherein each vertical plate comprises multipleconducting strips; the conducting strips are substantially parallel toeach other and are connected to each other by one or more vias; and thevertical plates are alternately connected to each other, creating afirst portion of the vertical plates and a second portion of thevertical plates, such that the first portion of the vertical platesforms a first terminal of the capacitor structure, and the secondportion of the vertical plates forms a second terminal of the capacitorstructure.
 2. The capacitor structure of claim 1, wherein slotted viasare used to connect conducting strips.
 3. The capacitor structure ofclaim 1, wherein individual vias are used to connect conducting strips.4. The capacitor structure of claim 1, wherein interleaving vias areused to connect conducting strips.
 5. The capacitor structure of claim1, wherein the conducting strips are metal conducting strips.
 6. Thecapacitor structure of claim 1, wherein the conducting strips arepoly-crystalline silicon strips.
 7. The capacitor structure of claim 1,wherein each vertical plate is located a predefined lateral distancefrom an adjacent vertical plate.
 8. A capacitor structure, comprising: aplurality of rows of vertical bars, wherein within each row, thevertical bars are substantially parallel to each other, and eachvertical bar comprises multiple conducting patches; the conductingpatches are connected to each other by one or more vias; the rows ofvertical bars form a first direction and a second direction, wherein thesecond direction is orthogonal to the first direction; in the firstdirection, the vertical bars are alternately connected to each other,creating a first portion of the vertical plates and a second portion ofthe vertical plates, such that the first portion of the vertical platesforms a section of the first terminal of the capacitor structure, andthe second portion of the vertical plates forms a section of the secondterminal of the capacitor structure; and in the second direction, thevertical bars are alternately connected to each other, creating a thirdportion of the vertical plates and a fourth portion of the verticalplates, such that the third portion of the vertical plates forms aremaining section of the first terminal of the capacitor structure, andthe fourth portion of the vertical plates forms a remaining section ofthe second terminal of the capacitor structure.
 9. The capacitorstructure of claim 8, wherein slotted vias are used to connectconducting strips.
 10. The capacitor structure of claim 8, whereinindividual vias are used to connect conducting strips.
 11. The capacitorstructure of claim 8, wherein the conducting strips are metal conductingstrips.
 12. The capacitor structure of claim 8, wherein the conductingstrips are poly-crystalline silicon strips.
 13. The capacitor structureof claim 8, wherein each vertical bar is located at a predefined lateraldistance from an adjacent vertical bar.
 14. The capacitor structure ofclaim 8, wherein each patch has a lateral size and the lateral sizeaffects the effective series resistance of the capacitor structure. 15.The capacitor structure of claims 8, wherein each patch has a lateralsize and the lateral size affects the quality factor of the capacitorstructure.
 16. A capacitor structure, comprising: in a first direction,a first layer comprising, a plurality of first layer vertical plates,wherein the first layer vertical plates are substantially parallel toeach other, and wherein each first layer vertical plate comprisesmultiple first layer conducting strips; the first layer conductingstrips are substantially parallel to each other and are connected toeach other by one or more first layer vias; the first layer verticalplates are alternately connected to each other, creating a first portionof the first layer vertical plates and a second portion of the firstlayer vertical plates, such that the first portion of the first layervertical plates forms a section of the first terminal of the capacitorstructure and the second portion of the first layer vertical platesforms a section of the second terminal of the capacitor structure; in asecond direction, wherein the second direction is orthogonal to thefirst direction, a second layer comprising, a plurality of second layervertical plates, wherein the second layer vertical plates aresubstantially parallel to each other, and wherein each second layervertical plate comprises multiple second layer conducting strips; thesecond layer conducting strips are substantially parallel to each otherand are connected to each other by one or more second layer vias; thesecond layer vertical plates are alternately connected to each other,creating a first portion of the second layer vertical plates and asecond portion of the second layer vertical plates, such that the firstportion of the second layer vertical plates forms a remaining section ofthe first terminal of the capacitor structure, and the second portion ofthe second layer vertical plates forms a remaining section of the secondterminal of the capacitor structure; and whereby, the second layer isoverlying the first layer in a top view.
 17. The capacitor structure ofclaim 16, wherein slotted vias are used to connect conducting strips.18. The capacitor structure of claim 16, wherein individual vias areused to connect conducting strips.
 19. The capacitor structure of claim16, wherein the conducting strips are metal conducting strips.
 20. Thecapacitor structure of claim 16, wherein the conducting strips arepoly-crystalline silicon strips.
 21. The capacitor structure of claim16, wherein each first layer vertical plate is located a predefinedlateral distance from an adjacent first layer vertical plate, andwherein each second layer vertical plate is located a predefined lateraldistance from an adjacent second layer vertical plate.
 22. A capacitorstructure, comprising: more than two layers of vertical plates, whereineach layer is positioned in the following manner, in a first direction,a previous layer comprising, a plurality of previous layer verticalplates, wherein the previous layer vertical plates are substantiallyparallel to each other, and wherein each previous layer vertical platecomprises multiple previous layer conducting strips; the previous layerconducting strips are substantially parallel to each other and areconnected to each other by one or more previous layer vias; the previouslayer vertical plates are alternately connected to each other, creatinga first portion of the previous layer vertical plates and a secondportion of the previous layer vertical plates, such that the firstportion of the previous layer vertical plates forms a section of thefirst terminal of the capacitor structure and the second portion of theprevious layer vertical plates forms a section of the second terminal ofthe capacitor structure; in a second direction, wherein the seconddirection is orthogonal to the first direction, a subsequent layercomprising, a plurality of subsequent layer vertical plates, wherein thesubsequent layer vertical plates are substantially parallel to eachother, and wherein each subsequent layer vertical plate comprisesmultiple subsequent layer conducting strips; the subsequent layerconducting strips are substantially parallel to each other and areconnected to each other by one or more subsequent layer vias; thesubsequent layer vertical plates are alternately connected to eachother, creating a first portion of the subsequent layer vertical platesand a second portion of the subsequent layer vertical plates, such thatthe first portion of the subsequent layer vertical plates forms aremaining section of the first terminal of the capacitor structure, andthe second portion of the subsequent layer vertical plates forms aremaining section of the second terminal of the capacitor structure; andwhereby, the subsequent layer is overlying the previous layer in a topview.
 23. The capacitor structure of claim 22, wherein slotted vias areused to connect conducting strips.
 24. The capacitor structure of claim22, wherein individual vias are used to connect conducting strips. 25.The capacitor structure of claim 22, wherein the conducting strips aremetal conducting strips.
 26. The capacitor structure of claim 22,wherein the conducting strips are poly-crystalline silicon strips. 27.The capacitor structure of claim 22, wherein each first layer verticalplate is located a predefined lateral distance from an adjacent firstlayer vertical plate, and wherein each second layer vertical plate islocated a predefined lateral distance from an adjacent second layervertical plate.